`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:12:42 03/01/2015 
// Design Name: 
// Module Name:    latch 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module latch(clock, inp, outp);
	input clock;
	input inp;
	output[7:0] outp;
	wire[7:0] inp;
	reg[7:0] outp;
	
	always @ (posedge clock) begin: LATCH
		outp <= inp;
	end
endmodule

module mux2_8(select, inpa, inpb, outp);
	input select;
	input inpa;
	input inpb;
	output outp;
	wire select;
	wire[7:0] inpa;
	wire[7:0] inpb;
	wire[7:0] outp;
	
	assign outp = (select) ? inpa : inpb;
endmodule

module mux4_8(select, inpa, inpb, inpc, outp);
	input select, inpa, inpb, inpc;
	output outp;
	wire [1:0] select;
	wire[7:0] inpa, inpb, inpc;
	wire[7:0] outp;
	
	mux2_8 block1(select[1], (select[0]? inpa : inpc), inpb, outp);
endmodule

module bdirlatch(inp, outp, bdir, oe, clock);
	input inp, oe, clock;
	inout bdir;
	output outp;
	wire [7:0] inp, outp, bdir, interconnect;
	wire oe, clock;
	
	latch latch_inst(clock, inp, interconnect);
	assign bdir = oe ? interconnect : 8'bZ;
	assign outp = bdir;
endmodule

module bdirlatch3(mport, porta, portb, portc, readoe, clock, select, portoe);
	inout mport, porta, portb, portc;
	input readoe, select, clock, portoe;
	wire [7:0] mport, porta, portb, portc;
	wire readoe;
	wire [1:0] select;
	wire [2:0] portoe;
	wire [7:0] conn1, conn2, conn3, mux_conn;
	
	bdirlatch bdir1(mport, conn1, porta, portoe[0], clock);
	bdirlatch bdir2(mport, conn2, portb, portoe[1], clock);
	bdirlatch bdir3(mport, conn3, portc, portoe[2], clock);
	mux4_8 mux(select, conn1, conn2, conn3, mux_conn);
	assign mport = readoe ? mux_conn : 8'bZ;
endmodule

module modeselect(mport, porta, portb, portc, mode);
	inout mport, porta, portb, portc;
	input mode;
	wire [7:0] mport, porta, portb, portc;
	wire [1:0] mode;
	reg [4:0] status;
	
	always @ * begin
		if (mode == 2'b11) begin
			status <= mport[4:0];
		end
	end
	

	bdirlatch3 meisterlatch(mport, porta, portb, portc, mode == 2'b10, mode == 2'b01, status[1:0], status[4:2]);
endmodule